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Datasheet, Confidential - D e t a i l e d D e s c r i p t i o n I C m o d e S e r i a l D a t a B u s
Figure 21. Data Transfer on I C Serial Bus
AS3665
2
Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The
master device must generate an extra clock pulse that is associated with this acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the
SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of course, setup and hold
times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge
bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to
enable the master to generate the STOP condition.
2
SDA
MSB
SLAVE
ADDRESS
R/W
DIRECTION
BIT
ACKNOWLEDGEMENT
SIGNAL FROM
RECEIVER
ACKNOWLEDGEMENT
SIGNAL FROM
RECEIVER
SCL
1
2
6
7
8
9
1
2
3-8
8
9
ACK
START
CONDITION
REPEATED IF
MORE BYTES ARE
TRANSFERRED
STOP CONDITION
OR REPEATED
START CONDITION
Depending upon the state of the R/W bit, two types of data transfer are possible:
1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the
slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received
byte. Data is transferred with the most significant bit (MSB) first.
2. Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the slave
address). The slave then returns an acknowledge bit, followed by the slave transmitting a number of data
bytes. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the
last received byte, a “not acknowledge” is returned. The master device generates all of the serial clock pulses
and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START
condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not
released. Data is transferred with the most significant bit (MSB) first.
The AS3665 can operate in the following two modes:
1. Slave Receiver Mode (Write Mode): Serial data and clock are received through SDA and SCL. After each
byte is received an acknowledge bit is transmitted. START and STOP conditions are recognized as the begin-
ning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave
address and direction bit (see Figure 22) . The slave address byte is the first byte received after the master
generates the START condition. The slave address byte contains the 7-bit AS3665 address, which is
1000XXX , followed by the direction bit (R/W), which, for a write, is 0.
10 11
After receiving and decoding the
10.’XXX’ depends on the external resistor R ADDR used; see I C Address selection on page 40
slave address byte the device outputs an acknowledge on the SDA line. After the AS3665 acknowledges the
slave address + write bit, the master transmits a register address to the AS3665. This sets the register pointer
on the AS3665. The master may then transmit zero or more bytes of data (if more than one data byte is written
2
11.The address for writing to the AS3665 is 8Xh = 1000XXX0b - see Table 53
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